• DocumentCode
    3686906
  • Title

    A systematic approach for diagnosing multiple delay faults

  • Author

    J.G. Dastidar;N.A. Touba

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    1998
  • Firstpage
    211
  • Lastpage
    216
  • Abstract
    In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach is proposed for delay fault diagnosis under a multiple fault assumption. Information from the failing test vectors are used to construct a list of single and multiple fault suspects that may have caused all of the observed faulty response. The list of suspects is then pruned and ranked in a novel way by using information from the passing test vectors combined with static timing information.
  • Keywords
    "Delay","Circuit faults","Fault diagnosis","Circuit testing","Timing","Read only memory","Logic circuits","Manufacturing","Integrated circuit technology","Clocks"
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
  • ISSN
    1063-6722
  • Print_ISBN
    0-8186-8832-7
  • Type

    conf

  • DOI
    10.1109/DFTVS.1998.732168
  • Filename
    732168