Design of ultra low power multipliers using hybrid adders

In this paper Low power multipliers can be designed by using new technique. This technique introduces new hybrid full adders and compressors. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates and inverters which were used in signed multipliers like Baugh-wooley multipliers, thereby lowering the power consumption and the total number of required transistors. In this paper 8×8 array multipliers, Baugh-Wooley multipliers are designed by using this hybrid adders and tree multipliers are designed by using compressors and the power, area, delay of these multipliers are compared. For an 8×8 implementation, the ALL-NAND array multiplier achieves reduction interms of power consumption and 7.8 % reduction in transistor count with increase in time delay compared to baugh-wooley multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and 7.3% reduction in transistor count, with longer time delay, compared to conventional tree multiplier. The simulation results are obtained by tsmc 0.18nm technology.