Area-reduced parallel FIR digital filter structures based on Modified Winograd Algorithm

This paper shows the implementation of 2-parallel 24 tap Finite Impulse Response Filter using Modified Winograd Algorithm. This technique is efficient in terms of area. This paper also analyses the filter performance using different adders like Carry Select Adder (CSA), Ripple Carry Adder (RCA) and Wallace Multiplier. Symmetric coefficient sub filter blocks are designed using inherent nature of symmetric filter coefficients. In symmetric coefficient sub filter block, the number of multiplier reduced to half. The structure is optimized by minimizing multipliers at the cost of additional adder in pre-processing and post processing blocks. Replacing multipliers with adders is always beneficial. Since silicon area required for multipliers is always less as compared to adders.