Title :
Design of low density parity check decoder using Min-Sum algorithm
Author :
Sachin S. Bhojane;Monica V. Mankar;Gajendra M. Asutkar;Pravin K. Dakhole
Author_Institution :
Yeshwantrao Chavan College of Engineering, an autonomous institute affiliated to Rashtrasant Tukadoji Maharaj Nagpur University, maharashtra India
fDate :
4/1/2015 12:00:00 AM
Abstract :
Low density parity check (LDPC) code has received more attention due to their excellent error correcting performance capabilities. An LDPC code can be decoded using iterative method like the sum-product algorithm and the Min-Sum algorithm based on its Tanner graph. In this paper, fully parallel architecture has been designed for LDPC decoder using Min-Sum algorithm. This decoder modeled in Verilog synthesized and performed place and route for design using Xilinx 13.1.
Keywords :
"Algorithm design and analysis","Decoding","Hardware design languages","Indexes","Communication standards","Sum product algorithm"
Conference_Titel :
Communications and Signal Processing (ICCSP), 2015 International Conference on
DOI :
10.1109/ICCSP.2015.7322560
