Design of stacking technique based DFAL frequency divider

Frequency dividers are crucial circuits that are employed in PLLs and high-speed serialize/deserializers. The flip-flop-based frequency dividers are comprised of two D latches in cascade, and in a negative feedback configuration. The digital operation of this type of dividers provides the advantage of suppressing the sensitivity to waveform distortions. Furthermore, the flip-flop-based dividers achieve a wide bandwidth than other types of frequency dividers at low-to-medium range of frequencies. Frequency dividers play an important role in high speed communications systems. In particular, optical communication circuits demand frequency dividers capable of operating well above 10 GHz. This paper presents a high-speed Stacking technique based DFAL frequency divider incorporating a new high-speed latch topology, which provides satisfactory performance for frequencies up to 17 GHz. This circuit is designed and simulated in a standard 0.18μm CMOS process. This architecture is primarily a master-slave flip-flop with a negative feedback. This circuit works by continually toggling the output state after every clock cycle. The mechanism effectively causes the output to toggle between one and zero at a rate half that of the input clock. Thus frequency division is achieved. The designed circuit and the verification can be done in TANNER EDA.