Synthesis of Advanced Encryption Standards using Xilinx 13.4

Secure System is significant part in the data communication. Randomization in the secret keys give raises to the security and complexity of the cryptography algorithms. However, the algorithms are compensating memory spaces and execution time. In Nov 2001 NIST select Advanced Encryption Standards (AES). Field programmable gate arrays (FPGAs), are reconfigurable in nature, low in price and. This paper proposes FPGA implementation of the 128-bits AES which is used to encrypt/decrypt block data using cipher key. This method is experimentally simulated by using 8 bit data path in VHDL using Xilinx ISE 13.4 based on FPGA technology.