Design of fast fourier transform using processing element for real valued signal

This brief presents an architecture for in-place fast Fourier transform (IFFT) computation for real valued signals. The proposed computation is based on modified radix-2 algorithm, which removes the redundant operations from the flow graph. The modified flow graph contains only real data paths as opposed to complex data paths in a regular flow graph. A new processing element (PE) is proposed which consists of two radix-2 butterflies that can process four inputs signals in parallel. A new conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. The addressing scheme is also used to support multiple parallel PEs. As the proposed PE processes the four parallel inputs that reduce computation cycles and increase the speed compared to prior work. The number of computation cycles is reduced with increase in the number of PEs. As redundant operations are removed, that reduces hardware cost.