Implementation of low power FIR filter using Sub-threshold boost logic design

This paper presents the implementation of FIR filter operating on 180MHz using Sub threshold boost logic. Sub threshold boost logic is one of the reliable charge recovery logic which gives high energy efficiency while operating on high frequencies. SBL facilitates operation of digital systems at high clock frequencies ranging from 180MHz-1GHz.Digital circuits like carry save adder, carry save multiplier and array multiplier has been implemented and compared with CMOS logic design and also with Enhanced Boost Logic. A 4-tap digital FIR filter has been designed and implemented using Industry standard Cadence Virtuoso-64. Simulation result shows that this design technique lowers energy consumption up to 10% to 15%.