Design and implementation of H/W efficient Multiplier: Reversible logic gate approach

Modern circuit design is starving for compact and low power dissipating devices with long life. So investigations are made to minimize all kinds of non-linearities even like heat dissipation by an individual circuit or a system like modern DSP. Irreversible logic circuit dissipates more heat for every bit of information that is lost. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. The reversible logic has received great attention in last few years due to their ability to decrease the power dissipation which is the main requirement in low power VLSI design. In this paper we have presented and implemented reversible Wallace signed multiplier circuit using pass transistor logic through modified Baugh-Woolley approach using standard reversible logic gate/cells, and have been validated with simulations. It has been made known that the designed multiplier is better and optimized compared to its existing with respect to the number of gates, garbage outputs and power dissipation. Schematics are drawn/simulated SymicaDE environment for different feature sizes.