Design of iterative data flow graph using hierarchical folding

Folding transformation systematically determines the control circuits in digital signal processing architectures which are described by data flow graph (DFG). For a specified folding set and technology constraints it gives architecture represented by hardware DFG. In iterative DFG which can be represented as cascade of similar substructures, rather than applying folding transformation on whole DFG, hierarchical folding folds one substructure and then folding is completed after appropriately changing the number of delays and switch instances in the resulted structure. This paper introduces two ways of applying hierarchical folding namely hierarchical interleaved folding and hierarchical contiguous folding. Its advantages signifies reduction in area required for implementation and run time. From experimental results it is proved that the area requirement and execution time is reduced for two stage sixth order infinite impulse response filter by hierarchical folding over conventional one.