Design of efficient double tail comparator for low power

Comparator is an important part of Analog to Digital Converter (ADC), used to find out whether input signal is high or low at each clock signal. A conventional comparator consisting of two cross-coupled inverters is modified for fast operation and low power by adding few transistors with multi-threshold voltage technology. Analysis of power and delay of dynamic comparator are presented. The advantage of this comparator is rail to rail output swing, no static power consumption and robustness against influence of mismatch. Simulation result in 0.18μm confirms reduction in power in proposed double tail comparator.