Improved block based processing with dual partial reconfiguration memory approach

Research on run time reconfiguration of FPGAs has been in academia for more than two decades, attempting to derive more benefits for FPGA based designs. The Dynamic Partial Reconfiguration (DPR) with runtime partial bit file loading capability was found to be more useful for designing flexible hardware. Majority of researchers found the limitations with DPR approach, due to higher configuration time. The research presented here proposes a dual configuration memory approach, which can increase the scope of DPR to several categories of applications. A novel dual reconfiguration memory based approach is proposed for efficient block based processing. The proposed architecture is analysed in the context of Frequency Shift Keying (FSK) demodulator architecture. The FSK demodulator functionality is achieved with 7 stages, where each stage configured as reconfigurable block. The memory controller and data pre processing blocks are used to preserve the context across each partial reconfiguration cycle. The proposed architecture matches the block processing time with partial reconfiguration time, so that the maximum throughput is achieved. Analysis results show that under given circumstances 91% rise in throughput is possible with dual reconfigurable memory approach. The improved dynamic partial reconfiguration shall enable realizing several signal processing algorithms on FPGAs, while occupying less area.