Comparison of conventional flip flops with pulse triggered generation using signal feed through technique

The objective is to design and simulate the high speed low power pulse triggered flip-flop and to reduce the dynamic power consumption of the flip flop by applying pulse triggering method used for the clocks. Since the on time of the clock pulses are narrowed down, the dynamic power dissipation of the flip flop is greatly reduced. Here, a dedicated pulse generation circuit is used to provide clock pulse with very short on time so that the flip flop switching time is reduced to achieve reduction in the dynamic power dissipation. The design is implemented in GPDK 90nm technology using Cadence Virtuoso Schematic Composer and the Spectre as the simulator.