Parallel RS Error Correction Structures Dedicated for 100 Gbps Wireless Data Link Layer

One of the most calculation intensive operations for a 100 Gbps wireless packet processing is a forward error correction (FEC). We are using standard field programmable gate arrays (FPGAs) to prepare a data link layer demonstrator. Therefore, we need to find a high-parallelized FEC structure for our device. The difficulty is to design the 100 Gbps FEC engine that can be realized in an FPGA. In one of previous papers, we have proposed a solution based on convolutional coding, but the engine consumed equivalent logic of 23 FPGAs [1]. That solution could not be implemented in nowadays FPGAs. In this paper, we propose parallel Reed-Solomon (RS) coders to reach the 100 Gbps throughput. The main task is to select the best candidates from available correction codes for the targeted 100 Gbps wireless communication and fit it to one or two high-end FPGAs. At the end, we demonstrate a system with two FPGAs, which is achieving continuous user data transfer rate of 97 Gbps and is negotiating the RS parameters according to the channel bit error rate.