RAM-based micro-architecture for a high-throughput interconnection network

A novel micro-architecture of an interconnection network is proposed which realizes a strictly non-blocking switch operation in three stages by employing word-wise circular-shift circuits and a number of small banks of dual-port (DP) static random access memory (SRAM). The interconnection network is controlled by a single, centralized controller, which distributes the words across the DP SRAM banks in a predefined fashion and uses a single configurable circular-shift circuit to apply the switch operation for a given input-output mapping. The proposed micro-architecture is strictly non-blocking and has a low, fixed-valued input-output latency. Its operation does not require traffic segmentation into uniformly-sized cells. Our analysis also indicates that this architecture is compact and energy-efficient when implemented in CMOS. The proposed architecture is suitable for a wide range of applications, from switch fabric in network switches and routers to computer interconnection networks and networks-on-a-chip.