New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering

We propose a new layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. In order to understand the impact of parasitics in monolithic 3D-stacked CMOS circuits, careful analysis of intra- and inter- layer parasitic capacitances were performed by using physics-based RC extractor for realistic 3D structure. As a result, we found that separation of power-supply (V_dd) and ground-line (GND) layer from logic elements is a key to reduce the parasitic capacitance thanks to be suppressed electrical coupling between stacked layers. By comparative evaluation among possible 3D layer configurations, we revealed that the best configuration is V_dd and GND layer sandwiched between nFET and pFET logic layers. Performance benchmarking by energy consumption-switching delay demonstrated that a 40% improvement of energy-delay product at V_dd = 0.5 V can be achieved by using a proposed layout methodology.