DocumentCode :
3689035
Title :
Back-gate effects and detailed characterization of junctionless transistor
Author :
Mukta Singh Parihar;Fan Yu Liu;Carlos Navarro;Sylvain Barraud;Maryline Bawedin;Irina Ionica;Abhinav Kranti;Sorin Cristoloveanu
Author_Institution :
IMEP-LAHC, INP Grenoble, MINATEC, 3 Parvis Louis Neel, CS 50257, 38016 Grenoble, France
fYear :
2015
Firstpage :
282
Lastpage :
285
Abstract :
The work addresses effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced FDSOI technology. A systematic methodology to extract and discriminate the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the properties of back channel in ultra-thin heavily doped JL devices. It has been demonstrated that both volume and accumulation-mode mobilities increase when the front surface is in accumulation.
Keywords :
"Decision support systems","Erbium"
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference (ESSDERC), 2015 45th European
ISSN :
1930-8876
Print_ISBN :
978-1-4673-7133-9
Electronic_ISBN :
2378-6558
Type :
conf
DOI :
10.1109/ESSDERC.2015.7324769
Filename :
7324769
Link To Document :
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