DocumentCode
3689793
Title
High performance Cu/low-k interconnect strategy beyond 10nm logic technology
Author
R.-H. Kim;B. H. Kim;J. N. Kim;J. J. Lee;J. M. Baek;J. H. Hwang;J. Hwang;J. Chang;S. Y. Yoo;T.-J. Yim;K.-M. Chung;K. H. Park;T. Oszinda;I S. Kim;E. B. Lee;S. D. Nam;S. Jung;Y. W. Cho;H. J. Choi;J. S. Kim;S. H. Ahn;S. H. Park;B. U. Yoon;J.-H. Ku;S. S. Paak;
Author_Institution
Semiconductor R&
fYear
2015
fDate
5/1/2015 12:00:00 AM
Firstpage
1
Lastpage
4
Abstract
CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.
Keywords
"Robustness","Scanning electron microscopy","Resistance","Performance evaluation","Failure analysis","Metals"
Publisher
ieee
Conference_Titel
Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), 2015 IEEE International
ISSN
2380-632X
Electronic_ISBN
2380-6338
Type
conf
DOI
10.1109/IITC-MAM.2015.7325599
Filename
7325599
Link To Document