Title :
Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing
Author :
K. Fischer;M. Agostinelli;C. Allen;D. Bahr;M. Bost;P. Charvat;V. Chikarmane;Q. Fu;C. Ganpule;M. Haran;M. Heckscher;H. Hiramatsu;E. Hwang;P. Jain;I. Jin;R. Kasim;S. Kosaraju;K. S. Lee;H. Liu;R. McFadden;S. Nigam;R. Patel;C. Pelto;P. Plekhanov;M. Prince;C.
Author_Institution :
Logic Technology Department, Corporate Quality Network Intel Corporation, 5200 Elam Young Pkwy, Hillsboro, OR 97124, USA
fDate :
5/1/2015 12:00:00 AM
Abstract :
We describe here Intel´s 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division patterning is introduced to deliver high yield capable interconnect layers with a minimum pitch of 52nm.
Conference_Titel :
Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), 2015 IEEE International
Electronic_ISBN :
2380-6338
DOI :
10.1109/IITC-MAM.2015.7325600
