Advanced integrated metallization enables 3D-IC TSV scaling

Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.