Variability of quadruple-patterning interconnect processes

This paper compares different patterning options for back-end of line interconnects by analyzing the impact of process variations on the line resistance and capacitance. Multiple sources of variation, such as overlay, CD, etch and CMP, are taken into account in the model. The model and variability parameters are validated using test chip measurements. Several quadruple patterning options for the 7nm process node are considered. Using 3D interconnect models and Monte-Carlo analysis, statistical metrics for the different patterning options are obtained. The analysis shows that the anti-spacer patterning approach has lowest variability and best uniformity.