Si interposer with high aspect ratio copper filled TSV for system integration

3D integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. Through silicon via (TSV) is one of the key elements for 3D integration. This paper presents different liner and barrier/seed approaches for realizing 10×100 um void-free copper filled TSVs. Mechanical and electrical performances of these liner and barrier/seed are also studied in order to give reliability guidelines for process optimization. It is found that the PECVD TEOS film shows high breakdown voltage, capacitance and low stepcoverage, while the thermal oxide film offers almost 100% stepcoverage and low leakage current. Hence thermal oxide/ PECVD TEOS bi-layer is formed to combine the advantage of each layer. A thin thermal oxide layer can also enlarge the Cu TSV backside reveal process window when Si is etched by HF contained solution. 2.5D integration of functional chips is finally achieved, from which good eye diagram is observed. For further scaling up the aspect ratio of TSV, novel barrier/seed deposition methods are also investigated and void-free Cu plating is successfully achieved.