DocumentCode :
3694111
Title :
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture
Author :
Sandro Belfanti;Christian Benkeser;Karim Badawi;Qiuting Huang;Andreas Burg
Author_Institution :
Integrated Systems Laboratory, ETH Zurich, 8092, Switzerland
fYear :
2012
Firstpage :
279
Lastpage :
282
Abstract :
This paper presents a VLSI implementation of an MMSE successive interference cancellation multiuser detector (SIC-MUD) for the downlink of a TD-SCDMA system. Computation in the frequency domain, group-wise interference cancellation, and pre-computation of filter coefficients enable an efficient architecture suitable for mobile handsets. Our implementation in 0.13µm CMOS technology proves that the SIC-MUD is a viable solution for the TD-SCDMA downlink, providing a notable performance gain at a moderate increase in complexity compared to linear equalizers.
Keywords :
"Finite impulse response filters","Time division synchronous code division multiple access","Interference","High definition video","Frequency-domain analysis","Equalizers","Silicon carbide"
Publisher :
ieee
Conference_Titel :
VLSI and System-on-Chip, 2012 (VLSI-SoC), IEEE/IFIP 20th International Conference on
Print_ISBN :
978-1-4673-2658-2
Type :
conf
DOI :
10.1109/VLSI-SoC.2012.7332117
Filename :
7332117
Link To Document :
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