Study of TLC application for 1 Mbit embedded non-overlapped implantation NVM

This work aims to develop the operation algorithm to improve the wide Vth distribution with the conventional program method and to achieve Triple-Level Cell (TLC) technology. The algorithm is used to enhance the convergence of the Vth distribution in the array. The Vth shift level of each NOI memory is controlled by the sequential programming and read out pulse. In this study, we accomplish three non-overlap states of Vt distribution in the total voltage window (TVW) of the NOI memory circuit. The results can keep the three non-overlap states of Vt distribution even through high temperature baking. In this way, the data can be stored into three different logic states in a single cell to achieve higher density storage ability in NOI memory array circuit.