Design of short channel static induction transistor for low power applications

A short channel normally-off static induction transistor (SIT) for low power applications is designed. Research about this SIT´s performance such as I-V characteristics, gate-source breakdown, gate-drain breakdown et al. is achieved by numerical simulation. Process parameters and structural parameters of SIT are optimized based on the simulation results. After tape-out we conduct the SIT´s performance testing and analysis, and compare it with 2SK79 produced by Sony Corporation. The results show that the performance of the SIT designed has been developed into the international advanced level. Specific parameter values are as follows: BVGSO = 24 V, BVGDO = 123.5 V, IGSO = 40 µA, IGDO = 70 µA, µ = 65, gm = 50–325 mS. Development cycle is shortened and the costs are reduced greatly by means of simulation.