Low power static induction transistor with high gate-control efficiency

A design method is proposed for obtaining high gate control efficiency SIT with surface-gate structure for low power Applications. In this paper a high performance SIT with comparatively large voltage amplification factor was manufactured and tested. Based on simulation and calculation, voltage amplification factor depends on not only the aspect ratio of the channel but also the impurity distribution in gate region. As a result, proper structural parameters and material parameters were chosen. In addition, ion implantation is adopted replacing diffusion, which makes the impurities step distribution in gate region. Experimental results have well consistent with our expectation.