Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors

Three-dimensional integrated circuit (3D IC) is one of the promising ways to enhance IC performance. Each IC chip is mechanically connected by organic adhesive and metal microbumps. Coefficient of thermal expansion (CTE) mismatch between materials causes local bending stress in IC chips, leading to negative effects in IC performance. In this study, we have fabricated a test structure with DRAM cell array having planar MOS capacitors. Using the test structure, we measured both DRAM chip bending profiles and retention time modulations of DRAM cell array. Consequently, we have successfully demonstrated that the local bending stress in IC chips can be two-dimensionally evaluated using the DRAM cell array with planar MOS capacitances. This evaluation methods leads to realization of 3D IC with high reliability.