DocumentCode
3695873
Title
Neuromorphic semiconductor memory
Author
Chung H. Lam
Author_Institution
IBM Research, Thomas Watson Research Center, Yorktown Heights, New York, USA
fYear
2015
Abstract
Microprocessors designed with von Neumann architecture are hitting the power and performance limits as silicon CMOS continues to scale the critical dimensions of the circuit components towards single digit nanometer size limit. Multi-core processor, parallel processing without increasing operating frequency of the cores, was introduced in the early 2000 to extend the power and performance scaling, keeping Moore´s Law viable. Evolution has provided us with the most efficient parallel processing architecture: the biological brain. In this talk, we shall examine what we can do with little that we know about how the brain works to design machines to mimic the brain´s memory.
Keywords
"Neuromorphics","Timing","Computer architecture","Microprocessors"
Publisher
ieee
Conference_Titel
3D Systems Integration Conference (3DIC), 2015 International
Type
conf
DOI
10.1109/3DIC.2015.7334566
Filename
7334566
Link To Document