Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC

Diminishing returns from transistor scaling, increasing interconnect delay, and the need for high device density and high energy efficiency are pushing the semiconductor industry in the direction of 3-dimensional integrated circuits (3DICs). In a 3DIC multiple active tiers are stacked vertically to make a single chip. Inter-tier signals are interconnected using through-silicon-vias or top-metal layer bondpoints (micro-bumps), called 3D-vias. In a traditional 2DIC I/O signals influence cell placement in the layout. Similar to I/O, inter-tier signals assigned to 3D-vias have a significant effect on standard cell placement, making the assignment very crucial for efficient 3DIC implementations. Our prior work presented techniques for automating the assignment procedure, but did not consider congestion and wiring requirements in the 3D-via assignment step. This work introduces congestion-and neighborhood-aware optimal techniques for assigning intertier signals to 3D-vias. The proposed methods provide globally and locally optimized techniques for assignment. Two 3DICs were built using the proposed local weights method which successfully automated the assignment process. The results obtained from post place-and-route layouts show lower total wire length (up to 7%) and average wire length (7.4%) as compared to an architecture-driven manual method. As demonstrated, 3DIC designs that have higher relative congestion between interconnecting tiers can benefit significantly from the proposed techniques.