SystemVerilog assertion debugging: A visualization and pattern matching model

Debugging a complex design is not an easy process. The more complex the design is, the more mistakes can be made, while writing an assertion. Regular expressions are widely used for text searching and replacement. Both regular expressions and three-state visual representation can be used simultaneously to validate and debug assertions. This paper presents a new methodology for debugging concurrent assertions based on a three-state visual representation and a new proposed pattern matching model. The proposed pattern matching model uses a new approach to validate assertions. The new approach performs parallel sequence items checking instead of serial checking of each sequence along time. The proposed new methodology assumes that error is just in the assertion and no errors are in the testbench or in the design. Experimental results show how much this methodology is effective that errors are analyzed and fixed within two minutes.