Multi-level Processing to Reduce Cost of Synchronization

Multi-Level Processing reduces the cost of synchronization overhead with an upper level processor for taking control and issuing the right to use shared data and to enter critical sections directly to each of lower level processors at processor speed. The instruction registers of lower level parallel processors are mapped to the data memory of upper level processor. The upper level processor has the ability to stretch the clock to reduce power consumption while processors are waiting. It can issue SIMD to multiple low level processors with no added cost to implementation. This system could be expanded to use three level of processing for large scale system.