Quantitative comparison of power-gating architectures for FinFET-based nonvolatile SRAM using spintronics retention technology

Power-gating (PG) architectures employing nonvolatile state/data retention are expected as a highly efficient static energy reduction technique for high-performance CMOS logic systems. In this paper, two types of PG architectures using nonvolatile retention, i.e., nonvolatile power-gating (NVPG) and normally-off (NOF), are systematically investigated for FinFET-based nonvolatile SRAM (NV-SRAM) using spintronics retention technology. In particular, using a performance index “break-even time”, the energy efficiency for the replacement of SRAM with NV-SRAM is quantitatively compared for the NVPG and NOF architectures.