• DocumentCode
    3697341
  • Title

    Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture

  • Author

    Peter Gadfort;Aravind Dasu;Ali Akoglu

  • Author_Institution
    Sensors and Electron Devices Directorate, US Army Research Laboratory, Adelphi, MD, USA
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    The one-dimensional Fast Fourier Transform (1D-FFT) is a fast method of computing the Discrete Fourier Transform (DFT) that is pervasive in signal processing applications. In this paper we present details on the mapping of the 1D-FFT on a power efficient 3D FPGA-DRAM architecture [1], with four data sizes: 256pt, 1024pt, 4096pt and 32768pt to achieve 29 GFLOPs/W with a 65nm technology.
  • Keywords
    "Field programmable gate arrays","Computer architecture","Three-dimensional displays","Random access memory","Energy efficiency","Adders","Ports (Computers)"
  • Publisher
    ieee
  • Conference_Titel
    Energy Efficient Electronic Systems (E3S), 2015 Fourth Berkeley Symposium on
  • Type

    conf

  • DOI
    10.1109/E3S.2015.7336816
  • Filename
    7336816
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3697341