• DocumentCode
    3697928
  • Title

    Frequency doublers with 10.2/5.2 dBm peak power at 100/202 GHz in 45nm SOI CMOS

  • Author

    Gang Liu;Jefy Jayamon;James Buckwalter;Peter Asbeck

  • Author_Institution
    University of California, San Diego, USA
  • fYear
    2015
  • fDate
    5/1/2015 12:00:00 AM
  • Firstpage
    271
  • Lastpage
    274
  • Abstract
    This paper presents frequency doublers with high output power for millimeter-wave applications. The circuits are fabricated using a 45nm SOI CMOS technology. A new circuit topology, combining a push-push doubler core with a cascaded stacked amplifier, has been implemented to increase the output power. The first doubler delivers 10.2 dBm peak power at 100 GHz output, with a 3-dB bandwidth from 88 to 104 GHz and DC-RF efficiency of 4.1%, while the second doubler has 5.2 dBm peak power at 202 GHz, with a 3-dB bandwidth from 180 to 212 GHz and DC-RF efficiency of 3.3%. To the authors´ knowledge, these are the highest powers reported for silicon frequency doublers in similar frequency ranges to date. The 200 GHz doubler also provides the highest on-chip power from a single-element signal generation circuit without power combining.
  • Keywords
    "Power generation","Transistors","Logic gates","CMOS integrated circuits","Power measurement","Probes","Bandwidth"
  • Publisher
    ieee
  • Conference_Titel
    Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE
  • Type

    conf

  • DOI
    10.1109/RFIC.2015.7337757
  • Filename
    7337757