DocumentCode :
3698515
Title :
Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited)
Author :
Srinivasa Banna
Author_Institution :
Advanced Device Architecture, Technology Research, GLOBALFOUNDRIES, 2600 Great America Way, Santa Clara, CA 95054
fYear :
2015
Firstpage :
1
Lastpage :
8
Abstract :
With the introduction of FinFET technology in mass production, more designs and complex designs are being ported on 22nm and 14nm/16nm FinFET transistors. However, all FinFET transistors are not made equal to offer best System-on-Chip (SoC) performance and power benefits. Careful selection of fin structural parameters is critical for best SoC performance. This paper discusses FinFET scaling challenges, their impact on SoC performance, key trade-offs and possible solutions for best SoC performance at current and future technology nodes.
Keywords :
"Logic gates","FinFETs","Metals","Substrates","Resistance","Layout"
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2015 IEEE
Type :
conf
DOI :
10.1109/CICC.2015.7338378
Filename :
7338378
Link To Document :
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