A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM

An area-efficient time-domain conversion technique is reported to achieve 10-GS/s, 6-bit resolution in 65-nm CMOS. The front-end single voltage-to-time converter (VTC) running at full speed obviates any clock-skew calibration often needed in time interleaved ADCs. The inherent folding effect of the time-to-digital converter (TDC) employing ring oscillator (RO) as quantizers helps significantly to lower the back-end complexity while providing a built-in dynamic element matching (DEM) feature. Fabricated in a 65-nm CMOS process, the prototype occupies a silicon area of 0.073 mm². The measured DNL and INL, thanks to the DEM, are +0.27/-0.28 LSBs and +0.48/-0.49 LSBs, respectively. The measured SFDR and SNDR are over 42 dB and 27 dB with a Nyquist input at 10 GS/s. The ADC achieves a FoM of 0.5 pJ/conversion-step.