A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS

A low-power transceiver architecture for die-to-die applications is presented. The proposed transceiver employs CMOS logic-style circuits and a passive equalizer in the transmitter to reduce the power consumption. Single-ended signaling without a shared reference voltage is used to minimize the number of required signal traces and packaging bumps. A transceiver prototype is fabricated in 28 nm STM FD-SOI CMOS technology and it operates at 20 Gb/s and 16.4 Gb/s data rates over different channels with 5.9 and 7.1 dB of loss relative to DC (10.7 and 12.9 dB total loss) at the Nyquist frequency while consuming 0.30 and 0.33 pJ/bit excluding clocking circuits, respectively.