Title :
SAR ADCs in parallel [time-interleaved] converter arrays
Author_Institution :
Analog Devices Inc., Wilmington, MA
Abstract :
• Time-interleaved SAR ADCs are a major focus of active development • Power and area efficiency of SAR architecture suits itself very well to interleaving • Architecture scale well with advancing CMOS process — Process-limited FOMS (jitter) improves with device speed • Many techniques have been needed to enable high-performance, high-speed interleaved systems.
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2015 IEEE
DOI :
10.1109/CICC.2015.7338441
