A novel switched-capacitor-filter based low-area and fast-locking PLL

A new low-area and fast-locking Phase Locked Loop (PLL) is presented. The proposed PLL employs a new switched capacitor (SC) filter that uses fractional charge integration to implement capacitor multiplication effect. The proposed (SC) filter has a time response similar to the traditional passive filter response while occupying much smaller area and without any impact on other PLL blocks design. The proposed PLL was built in a 65nm CMOS process with a capacitance multiplication factor of 16 in parallel with a traditional filter for performance comparison. The PLL has an operating frequency range of 200MHz to 2.0GHz. Using a ring oscillator the PLL has period jitter in the order of 0.9ps RMS with acquisition time less than 10uS. Traditional LPF area is 180μm × 340μm while the (SC) LPF area is only 104μm × 84μm cutting LPF area by a factor 7.