Title :
Nanoscale SiGe BiCMOS technologies: From 55 nm reality to 14 nm opportunities and challenges
Author :
P. Chevalier;G. Avenier;E. Canderle;A. Montagné;G. Ribes;V.T. Vu
Author_Institution :
STMicroelectronics, Silicon Technology Development, 38926 Crolles, France
Abstract :
This paper looks back to the development of highspeed BiCMOS technologies in STMicroelectronics for the past 15 years and discusses the perspectives for next generations through the CMOS angle. Opportunities and challenges of nanoscale BiCMOS technologies are reviewed and BiCMOS055 results are presented to demonstrate the feasibility at 55 nm node. Perspectives to offer FDSOI BiCMOS technologies at 28 nm or 14 nm nodes are analyzed too.
Keywords :
"CMOS integrated circuits","BiCMOS integrated circuits","Silicon germanium","Heterojunction bipolar transistors","Logic gates","CMOS technology"
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting - BCTM, 2015 IEEE
DOI :
10.1109/BCTM.2015.7340556
