A DLL-based test solution for through silicon via (TSV) in 3D-stacked ICs

This study presents a new test method for Through Silicon Via (TSV) in 3D stacked ICs, in which a Delay-Locked Loop (DLL) is utilized to detect TSV defects. As compared to TSV test methods using free running ring oscillators, the proposed method presents a much better performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLL systems. In the proposed scheme, a periodic signal is applied to the TSV under test and the propagation delay is measured to detect TSV faults. To perform circuit level simulations, 3D full-wave simulations are performed to extract accurate spice models for both faulty and fault free TSVs. Simulation results indicate that the proposed test solution can detect TSV manufacturing defects, changing its propagation delay by more than 10% from the nominal value.