Optimizing delay tests at the memory boundary

Delay faults on the inputs and outputs of memories embedded in an integrated circuit are difficult to cover efficiently in manufacturing test. A complicated approach, separate from standard digital logic tests or memory built-in self-test, is needed to target these faults and further improve manufacturing quality. This paper discusses some of the challenges of implementing this approach and the design-for-test changes we made to the memories and to the surrounding logic to address these challenges. Our optimized method for testing the boundaries of repaired memories is presented. Our implementation has been validated and is included in our standard manufacturing test suite. It improves tests for delay faults on the memory functional boundary by minimizing the capture of unknown data, simplifying the test sequences, and testing different memory types in parallel. Results from five 32nm industry parts show that our method enables entirely automatic generation of a compact set of high-coverage test patterns for any integrated circuit design.