Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist

As CMOS technologies enter nanometer scales, maintaining the microprocessor reliability becomes a major design challenge. In particular, accelerated transistor aging is a serious reliability concern, as it considerably reduces the operational microprocessor lifetime. To address this issue, in this work cross-layer solutions for aging modeling and simulation as well as mitigation are investigated and proposed, to be able to co-optimize reliability together with the traditional design constraints such as power, performance, and cost. Therefore, the knowledge from several abstraction layers, ranging from circuit to architecture-level, are exploited for cost-effective aging-aware micro-architecture design. The detailed simulations and experimental analysis performed in this work show the benefits of this approach over state-of-the-art single-layer solutions.