Challenging factors of pipelined ADC design at higher speed and resolution

In the field of CMOS Integrated Circuits (IC), there are several types of Analog to Digital Converters (ADC). Every architecture rules its own region of operating conditions. The high level parameters which categorize ADC´s are Speed and Resolution. Pipelined ADC rules the region where the Speed and Resolution are moderate. More specifically, Resolution varies from 8 to 16 Bits, Speed varies from 10´s of MHz to 100´s of MHz. The pipelined ADC consist of various design blocks like fully differential amplifier, comparator, switch network etc.,. This paper details the major challenges on designing these blocks of pipelined ADC. This study has been carried out as a part of 10 Bit 100 Msps pipelined ADC design. This analysis is supported with spice simulations using CMOS 130 nm technology.