Energy saving dynamic level scheduling with energy estimation and monitoring in homogeneous multiprocessor system

In real time wireless embedded devices such as sensor network, laptop, cell phones, etc. Where functionalities are increasing exponentially, so computational power also increases exponentially. So they need high-performance processors. To fulfill this demand multiprocessor architectures are coming into existence where parallel program can be execute with minimizing total execution time or makespan. Such multiprocessor architectures require efficient algorithms to schedule the parallel tasks that can minimize the makespan, as well as Power consumption. In this paper, we address the problem of scheduling Directed Acyclic Precedence Graph (DAPG) on multiprocessor architecture with the objective of minimizing the Energy related to IPC (E_IPC). We propose a new scheduling heuristic called as Energy Saving Dynamic Level Scheduling (ESDLS) which accounts for E_IPC consumption. This algorithm is based on well-known compile time Dynamic Level Scheduling (DLS) algorithm that accounts for IPC overhead while mapping DAPG on to homogeneous multiprocessor architecture.