High speed latched comparator in 0.35um CMOS process

Comparator is the main building block in ADC architecture. Main purpose of a comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. In this paper, a high speed high resolution comparator for use in sigma delta modulator is designed. The comparator is designed in a 0.35 um CMOS process with a supply voltage of 3.3 V. Various non-linearities and performance parameters are discussed in detail. The design of latched comparator for sigma delta modulator is presented in detail. Design equations of different blocks of the comparator are derived and simulations were done on the different blocks.