Design and analysis of low-power high-speed clocked digital comparator

The need for low power, area efficient and high speed comparator is pushing towards the use of clocked digital comparator which maximize speed and power efficiency. As CMOS technology scales down, various short channel effects arises which increases the leakage current due to low threshold voltage and waste some percentage of power as leakage power. This paper presents detail survey of low power techniques and also proposed a new technique which modified the clocked digital comparator by adding some sleep transistors with appropriate W I´L ratio for low-power and fast operation. Various Post layout simulation result with 90nm, 65nm and 45nrn CMOS technology at supply voltage of 1.2 V confirms the analysis results. The result shows that in the proposed clocked Digital comparator both the Average power dissipation, delay time are significantly reduced. For maximum clock frequency of 500 MHz and offset voltage of 0.6 V, the proposed design-I comparator consumes 5.691/xW, 3.056 fj, W and 2.276 yW at 90nm, 65nm and 45nm respectively.