Design of high-speed power efficient full adder with body-biasing

A new 1-bit full adder cell has been introduced in this paper. According to this approach body-biasing and semi domino logic both are used in a single full adder. Body-biasing technique is used to vary the threshold voltage to operate this adder at higher speed by allowing the faster gate switching. The important thing in this approach is that there is no requirement of any external circuitry for body-biasing. Also, the power consumption of the proposed full adder circuit is very low by using the lower power supply and semi domino logic. Proposed design circuit is 1.5 to 2 times faster than the dynamic gate-level body biased design. The circuit design and analysis are carried out at 45 nm technology in SILVACO-ICCAD environment. The proposed design has lower energy consumption per operation and robust against process and temperature variation.