Latency reduction for LTE/LTE-A turbo-code decoders by on-the-fly calculation of CRC

The major challenge for the development of Turbo-Code decoders for the 3GPP LTE/LTE-A standard is the support of very high code rates while achieving a high throughput with a low decoding latency. For high code rates the decoding process can oscillate, i.e. although the decoder converges to a valid code word in the nth half-iteration, the code word after the n+1th half iteration can be invalid again. Thus, the CRC must be evaluated after every half-iteration to avoid a loss in communications performance. We propose a new CRC calculation scheme that takes into account requirements for parallel Turbo-Code decoding for LTE/LTE-A by calculating the CRC On-the-fly not only during the non-interleaved but also during the interleaved half-iterations. Further, we present a flexible hardware architecture that allows a reduction of the latency for the CRC calculation of up to 34× and is two times more area efficient with respect to latency when compared to State-of-the-Art.