A compact 105?130 GHz push-push doubler, with 4dBm Psat and 18% efficiency in 28nm CMOS

A high power doubler design for F-band frequencies, which covers 105-130 GHz, has been designed in low voltage process 1.1 V, 28nm CMOS. A new approach for shorting the 2nd harmonic in the input network and balancing the input balun at the fundamental frequency have been proposed for shrinking the doubler size. The doubler shows a peak output power of +4 dBm at 120 GHz with 18% efficiency at a bias voltage of 0V, and a peak gain of -2.2 dB, and occupy a size of a 0.03mm2. First pass success was achieved by running full EM simulation with component extractions resulting in excellent measurement fit to simulations.